CPU Infos

4 Input OR gate

AND

NAND

NOR1

NOR2

TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally equivalent to multiple transistors where the bases and collectors are tied together.^[11] The output is buffered by a common emitter amplifier.

Input logical ones. When all the inputs are held at high voltage, the base–emitter junctions of the multiple-emitter transistor are backward-biased. In contrast with DTL, small (about 10 μA) "collector" currents are drawn by the inputs since the transistor is in a reverse-active mode(with swapped collector and emitter). The base resistor in combination with the supply voltage acts as a substantially constant current source.^[2] It passes current through the base–collector junction of the multiple-emitter transistor and the base–emitter junction of the output transistor thus turning it on; the output voltage becomes low (logical zero).

Input logical zero. If one input voltage becomes zero, the corresponding base–emitter junction of the multiple-emitter transistor connects in parallel to the two connected in series junctions (the base–collector junction of the multiple-emitter transistor and the base–emitter junction of the second transistor). The input base–emitter junction steers^[12] all the base current of the output transistor to the input source (the ground). The base of the output transistor is deprived of current causing it to go into cut-off^[13] and the output voltage becomes high (logical one). During the transition the input transistor is briefly in its active region; so it draws a large current away from the base of the output transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that speeds up the transition over a diode input structure.^[14]

The main disadvantage of TTL with a simple output stage is the relatively high output resistance at output logical "1" that is completely determined by the output collector resistor. It limits the number of inputs that can be connected (the fanout). Some advantage of the simple output stage is the high voltage level (up to V_CC) of the output logical "1" when the output is not loaded.

Logic of this type is most frequently encountered with the collector resistor of the output transistor omitted, making an open collectoroutput. This allows the designer to fabricate logic by connecting the open collector outputs of several logic gates together and providing a single external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting), the combined output will be low. Examples of this type of gate are the 7401^[15] and 7403 series.

8 bit shifter

Octal D type Flip-Flops

D flip-flop

8 bits addition

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8 bits soustraction

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Binary numbers

Electronic circuits count in binary. This is the simplest possible counting system because it uses just two digits, 0 and 1, exactly like logic signals where 0 represents false and 1 represents true. The terms low and high are also used for 0 and 1 respectively as shown in the table.

Counting one, two, three, four, five in binary: 1, 10, 11, 100, 101.

Binary numbers rapidly become very long as the count increases and this makes them difficult for us to read at a glance. Fortunately it is rarely necessary to read more than 4 binary digits at a time in counting circuits.

In a binary number each digit represents a multiple of two (1, 2, 4, 8, 16 etc), in the same way that each digit in decimal represents a multiple of ten (1, 10, 100, 1000 etc).
For example 10110110 in binary equals 182 in decimal:

Digit value:	128		64		32		16		8		4		2		1
Binary number:	1		0		1		1		0		1		1		0
Decimal value:	128	+	0	+	32	+	16	+	0	+	4	+	2	+	0	=	182

Bits, bytes and nibbles

Each binary digit is called a bit, so 10110110 is an 8-bit number.

A block of 8 bits is called a byte and it can hold a maximum number of 11111111 = 255 in decimal. Computers and PIC microcontrollers work with blocks of 8 bits. Two (or more) bytes make a word, for example PICs work with a 16-bit word (two bytes) which can hold a maximum number of 65535.

A block of 4 bits is called a nibble (half a byte!) and it can hold a maximum number of 1111 = 15 in decimal. Many counting circuits work with blocks of 4 bits because this number of bits is required to count up to 9 in decimal. (The maximum number with 3 bits is only 7).

Hexadecimal (base 16)

Hexadecimal (often just called 'hex') is base 16 counting with 16 digits. It starts with the decimal digits 0-9, then continues with letters A (10), B (11), C (12), D (13), E (14) and F (15). Each hexadecimal digit is equivalent to 4 binary digits, making conversion between the two systems relatively easy. You may find hexadecimal used with PICs and computer systems but it is not generally used in simple counting circuits.

Example: 10110110 binary = B6 hexadecimal = 182 decimal.

Infos about how work a CPU

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Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. Depending on the specific application, a compromise of one of these requirements may be necessary in order to improve another requirement.

For example, dynamic memory is commonly used for primary data storage due to its fast access speed. However dynamic memory must be repeatedly refreshed with a surge of current millions of time per second, or the stored data will decay and be lost. Flash memory allows for long-term storage over a period of years, but it is much slower than dynamic memory, and the static memory storage cells wear out with frequent use.

Similarly, the data bus is often designed to suit specific needs such as serial or parallel data access, and the memory may be designed to provide for parity error detection or even error correction in expensive business systems.

ISA=Industry Standard Architecture

Pin	Name	Dir	Description
A1	/I/O CH CK		I/O channel check; active low=parity error
A2	D7		Data bit 7
A3	D6		Data bit 6
A4	D5		Data bit 5
A5	D4		Data bit 4
A6	D3		Data bit 3
A7	D2		Data bit 2
A8	D1		Data bit 1
A9	D0		Data bit 0
A10	I/O CH RDY		I/O Channel ready, pulled low to lengthen memory cycles
A11	AEN		Address enable; active high when DMA controls bus
A12	A19		Address bit 19
A13	A18		Address bit 18
A14	A17		Address bit 17
A15	A16		Address bit 16
A16	A15		Address bit 15
A17	A14		Address bit 14
A18	A13		Address bit 13
A19	A12		Address bit 12
A20	A11		Address bit 11
A21	A10		Address bit 10
A22	A9		Address bit 9
A23	A8		Address bit 8
A24	A7		Address bit 7
A25	A6		Address bit 6
A26	A5		Address bit 5
A27	A4		Address bit 4
A28	A3		Address bit 3
A29	A2		Address bit 2
A30	A1		Address bit 1
A31	A0		Address bit 0
B1	GND	 	Ground
B2	RESET		Active high to reset or initialize system logic
B3	+5V	 	+5 VDC
B4	IRQ2		Interrupt Request 2
B5	-5VDC	 	-5 VDC
B6	DRQ2		DMA Request 2
B7	-12VDC	 	-12 VDC
B8	/NOWS		No WaitState
B9	+12VDC	 	+12 VDC
B10	GND	 	Ground
B11	/SMEMW		System Memory Write
B12	/SMEMR		System Memory Read
B13	/IOW		I/O Write
B14	/IOR		I/O Read
B15	/DACK3		DMA Acknowledge 3
B16	DRQ3		DMA Request 3
B17	/DACK1		DMA Acknowledge 1
B18	DRQ1		DMA Request 1
B19	/REFRESH		Refresh
B20	CLOCK		System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21	IRQ7		Interrupt Request 7
B22	IRQ6		Interrupt Request 6
B23	IRQ5		Interrupt Request 5
B24	IRQ4		Interrupt Request 4
B25	IRQ3		Interrupt Request 3
B26	/DACK2		DMA Acknowledge 2
B27	T/C		Terminal count; pulses high when DMA term. count reached
B28	ALE		Address Latch Enable
B29	+5V	 	+5 VDC
B30	OSC		High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
B31	GND	 	Ground

 	 	 	 
C1	SBHE		System bus high enable (data available on SD8-15)
C2	LA23		Address bit 23
C3	LA22		Address bit 22
C4	LA21		Address bit 21
C5	LA20		Address bit 20
C6	LA18		Address bit 19
C7	LA17		Address bit 18
C8	LA16		Address bit 17
C9	/MEMR		Memory Read (Active on all memory read cycles)
C10	/MEMW		Memory Write (Active on all memory write cycles)
C11	SD08		Data bit 8
C12	SD09		Data bit 9
C13	SD10		Data bit 10
C14	SD11		Data bit 11
C15	SD12		Data bit 12
C16	SD13		Data bit 13
C17	SD14		Data bit 14
C18	SD15		Data bit 15
D1	/MEMCS16		Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2	/IOCS16		I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3	IRQ10		Interrupt Request 10
D4	IRQ11		Interrupt Request 11
D5	IRQ12		Interrupt Request 12
D6	IRQ15		Interrupt Request 15
D7	IRQ14		Interrupt Request 14
D8	/DACK0		DMA Acknowledge 0
D9	DRQ0		DMA Request 0
D10	/DACK5		DMA Acknowledge 5
D11	DRQ5		DMA Request 5
D12	/DACK6		DMA Acknowledge 6
D13	DRQ6		DMA Request 6
D14	/DACK7		DMA Acknowledge 7
D15	DRQ7		DMA Request 7
D16	+5 V	 	 
D17	/MASTER		Used with DRQ to gain control of system
D18	GND	 	Ground

The AT version of the bus is upwardly compatible, which means that cards designed to work on an XT bus will work on an AT bus. This bus was produced for many years without any formal standard. In recent years, a more formal standard called the ISA bus (Industry Standard Architecture) has been created, with an extension called the EISA (Extended ISA) bus also now as a standard. The EISA bus extensions will not be detailed here. This file is not intended to be a thorough coverage of the standard. It is for informational purposes only, and is intended to give designers and hobbyists sufficient information to design their own XT and AT compatible cards. Physical Design: ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses the first 62 pins and 16-bit cards uses all 98 pins. Some 8-bit cards uses some of the 16-bit extension pins to get more interrupts.

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The 6502 CPU has a 16 bit address bus and an 8 bit data bus.
It is powered by a 5 volt supply.
Interrupt requests tell the CPU to stop processing its present program and jump to another.
The reset pin is taken low to initialize the CPU when it is first powered on.
The read/write pin is taken low when writing to memory, and high when reading from it.The 6502 has eight addressing modes telling the CPU where data is located.

/MM controls a multiplexer that either selects the mapped address lines as output (map mode), or feeds the input address lines through to MO8-11 setting the other lines to zero (pass mode). This input thus enables or disables the mapping.

During read operation the mapped address lines are feed back to the input D0-11 to allow reading by the CPU. /CS must be low and R/-W must be high.

During write operation /CS must be low, as well as R/-W. In addition /Strobe must be low too. This input can be used for additional timing.

Programming the 65816

Apple IIgs Technical Notes

ADC	....	add with carry
AND	....	and (with accumulator)
ASL	....	arithmetic shift left
BCC	....	branch on carry clear
BCS	....	branch on carry set
BEQ	....	branch on equal (zero set)
BIT	....	bit test
BMI	....	branch on minus (negative set)
BNE	....	branch on not equal (zero clear)
BPL	....	branch on plus (negative clear)
BRK	....	interrupt
BVC	....	branch on overflow clear
BVS	....	branch on overflow set
CLC	....	clear carry
CLD	....	clear decimal
CLI	....	clear interrupt disable
CLV	....	clear overflow
CMP	....	compare (with accumulator)
CPX	....	compare with X
CPY	....	compare with Y
DEC	....	decrement
DEX	....	decrement X
DEY	....	decrement Y
EOR	....	exclusive or (with accumulator)
INC	....	increment
INX	....	increment X
INY	....	increment Y
JMP	....	jump
JSR	....	jump subroutine
LDA	....	load accumulator
LDY	....	load X
LDY	....	load Y
LSR	....	logical shift right
NOP	....	no operation
ORA	....	or with accumulator
PHA	NOP	....	no operation
ORA	....	or with accumulator
PHA	....	push accumulator
PHP	....	push processor status (SR)
PLA	....	pull accumulator
PLP	....	pull processor status (SR)
ROL	....	rotate left
ROR	....	rotate right
RTI	....	return from interrupt
RTS	....	return from subroutine
SBC	....	subtract with carry
SEC	....	set carry
SED	....	set decimal
SEI	....	set interrupt disable
STA	....	store accumulator
STX	....	store X
STY	....	store Y
TAX	....	transfer accumulator to X
TAY	....	transfer accumulator to Y
TSX	....	transfer stack pointer to X
TXA	....	transfer X to accumulator
TXS	....	transfer X to stack pointer
TYA	....	transfer Y to accumulator

Registers:

PC	....	program counter	(16 bit)
AC	....	accumulator	(8 bit)
X	....	X register	(8 bit)
Y	....	Y register	(8 bit)
SR	....	status register [NV-BDIZC]	(8 bit)
SP	....	stack pointer	(8 bit)

SR Flags (bit 7 to bit 0):

N	....	Negative
V	....	Overflow
-	....	ignored
B	....	Break
D	....	Decimal (use BCD for arithmetics)
I	....	Interrupt (IRQ disable)
Z	....	Zero
C	....	Carry

0001 0000 KEEP KL.12.5
0002 0000 65816 ON
0003 0000
0004 0000 PRSTRNG START
0005 0000
0006 0000 18 CLC
0007 0001 FB XCE
0008 0002
0009 0002 E220 SEP #$20 8-bit accum
0010 0004 LONGA OFF
0011 0004
0012 0004 C210 REP #$10 16-bit index regs
0013 0006 LONGI ON
0014 0006
0015 0006 FA PLX pull return address
0016 0007 E8 INX and increment to point JSR to string
0017 0008 BD0000 LOOP LDA !0,X get char at index position in string
0018 000B F006 BEQ DONE if character is 0, return
0019 000D 200080 JSR COUT print char in accum
0020 0010 E8 INX point to next char
0021 0011 80F5 BRA LOOP loop thru string
0022 0013
0023 0013 ; push pointer to zero-terminator as return addr (RETURN-1)
0024 0013
0025 0013 DA DONE PHX
0026 0014 60 RTS return to label RETURN
0027 0015 END
0028 0000
0029 0000
0030 0000 ; COUT
0031 0000 ; machine-dependent routine to output a character
0032 0000 ;
0033 0000 COUT START
0034 0000 ECOUT GEQU $FDED Apple / / COUT
0035 000 48 PHA Save registers
0036 0001 DA PHX
0037 0002 5A PHY
0038 0003 08 PHP and status,
0039 0004 38 SEC switch to emulation
0040 0005 FB XCE
0041 0006 20EDFD JSR ECOUT call 6502 routine
0042 0009 18 CLC
0043 000A FB XCE restore native mode
0044 000B 28 PLP restore status
0045 000C 7A PLY restore registers
0046 000D FA PLX return
0047 000E 68 PLA
0048 000F 60 RTS
0049 0010 END

SNES Memory Map in LoROM Mode (Mode 0x20):

Bank:	Address:	Purpose:
-----	--------	--------
00-3F	0000-1FFF	Shadow RAM
	2000-5FFF	Hardware Registers
	6000-7FFF	Expansion RAM
	8000-FFFF	32k ROM Chunk
40-7C	0000-7FFF	32k ROM Chunk
	8000-FFFF	32k ROM Chunk
7D	0000-FFFF	SRAM
7E	0000-1FFF	Shadow RAM
	2000-FFFF	System RAM
7F	0000-FFFF	System RAM

80-BF	0000-1FFF	Shadow RAM
	2000-5FFF	Hardware Registers
	6000-7FFF	Expansion RAM
	8000-FFFF	32k ROM Chunk
C0-FC	0000-7FFF	32k ROM Chunk
	8000-FFFF	32k ROM Chunk
FD	0000-FFFF	SRAM
FE	0000-1FFF	Shadow RAM
	2000-FFFF	System RAM
FF	0000-FFxx	System RAM
	FFxx-FFFF	Reset and NMI Vectors

SNES Memory Map in HiROM Mode (Mode 0x21):

Bank:	Address:	Purpose:
-----	--------	--------
00-3F	0000-1FFF	Shadow RAM
	2000-5FFF	Hardware Registers
	6000-7FFF	SRAM
	8000-FFFF	32k ROM Chunk
40-7D	0000-FFFF	64k ROM Chunk
7E	0000-1FFF	Shadow RAM
	2000-FFFF	System RAM
7F	0000-FFFF	System RAM

80-BF	0000-1FFF	Shadow RAM
	2000-5FFF	Hardware Registers
	6000-7FFF	SRAM
	8000-FFFF	32k ROM Chunk
C0-FE	0000-FFFF	64k ROM Chunk
FF	0000-FFxx	64k ROM Chunk
	FFxx-FFFF	Reset and NMI Vectors

SNES Test Program.zip

Infos on CPU

by Denis Verreault

Logical Gate

Electronic Shema

CPU Disigned

Binary numbers

Bits, bytes and nibbles

Hexadecimal (base 16)

Infos about how work a CPU

Z80 CPU

Z80 diagram

PC memory map

ISA pinout

6502

6502 complet diagram

6502 MMU

65C816 (16 bits)

65C816 Difference

Programming the 65816

Apple IIgs memory map

CY62157E 8-mbit 512k X 16 Static Ram

6502 Assembly language

65Cx example

Snes Memory Map

Snes video system

VIC 6567 electronic

YM3812 Techical data (sound)

Sound Blaster 16 I/O

5 Software to crack (challenge)